A computer system typically includes a processor and a chipset. The chipset may include one or more switches linking peripheral components via a number of buses to the processor. Peripheral Component Interconnect (“PCI”) is a standard developed to provide a data path between the peripheral components within the system. As the speed of processors advances, standards that provide high-speed data path within a computer system are developed, such as PCI-X and PCI Express™.
A PCI Express™ compatible switch with multiple ports appears to PCI compatible enumeration and configuration software as a two level hierarchy of PCI-to-PCI bridges. Each switch port appears to the configuration software as a distinct PCI-to-PCI bridge. Each port can support up to eight sub-functions, each sub-function potentially introducing a linked list of supported capabilities. Among the ports, there is an upstream port. The upstream port, which appears to software as a PCI-to-PCI bridge, is the only port through which PCI compatible software can read and/or write the internal configuration registers of the switch. All other ports of the switch, referred to as downstream ports, appear as distinct PCI-to-PCI bridges to the configuration software. As a result, a two-level hierarchy of PCI-to-PCI bridges is formed.
To configure the switch, the configuration software reads a configuration record stored in a set of configuration registers and writes to some of the configuration registers. An example of a configuration record stored in a set of configuration registers is shown in FIG. 1. The size of the configuration registers is constrained by the address of the configuration registers, which is 8-bit wide. Therefore, the set of configuration registers is limited to storing 28 bytes, i.e., 256 bytes of information, such as vendor ID, PCI status, class code, etc.
Since every port of the switch, including the upstream port, appears as a distinct PCI-to-PCI bridge, each port is represented by its own separate and distinct configuration register space. To support an additional port in the switch, one has to create an additional PCI-to-PCI bridge with its associated configuration register space. Creating a configuration register space for every port adds additional silicon cost and complexity to switch components.